module ONCHIPRAM(address, clock, data, wren, q);

    input [7:0] address;
    input clock;
    input [15:0] data;
    input wren;
    output reg [15:0] q;

    integer c;

    reg [15:0] ramblock [255:0];

    always @(posedge clock) begin
        if (wren) begin
            if (address) begin
                ramblock[address] = data;
            end
        end
        if (address) begin
            q <= ramblock[address];
        end
    end

endmodule

module counter(clk, rst, out);
    input clk;
    input rst;
    output reg [7:0] out;

    always @(posedge clk) begin
        if (rst) begin
            out <= 1'b0;
        end else begin
            out <= out + 8'b1;
        end
    end
endmodule

module test();
    reg clk;
    reg gres;
    reg wren;
    wire [7:0] address;
    wire [15:0] q;

    initial begin        
        $dumpfile("mem.vcd");
        $dumpvars(0, clk, gres, wren, address, q);
        #0 clk <= 0;
        #0 gres <= 1;
        #0 wren <= 0;
        #50 gres <= 0;
        #0 wren <= 1;
        #2500 $finish;
    end

    always begin
        #10 clk <= ~clk;
    end

    counter cnt(.clk(clk)
        , .rst(gres)
        , .out(address)
    );

    ONCHIPRAM    ram (
        .address ( address ),
        .clock ( clk ),
        .data ( {address, address} ),
        .wren ( wren ),
        .q ( q )
    );
endmodule

ramblock[address] <= data;